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? semiconductor components industries, llc, 2011 october, 2011 ? rev. 4 1 publication order number: ncv5171/d ncv5171, ncv5173 1.5 a 280 khz/560 khz boost regulators the ncv5171/73 products are 280 khz/560 khz switching regulators with a high efficiency, 1.5 a integrated switch. the parts operate over a wide input voltage range, from 2.7 v to 30 v. the flexibility of the design allows the chip to operate in most power supply configurations, including boost, flyback, forward, inverting, and sepic. the ics utilize current mode architecture, which allows excellent load and line regulation, as well as a practical means for limiting current. combining high frequency operation with a highly integrated regulator circuit results in an extremely compact power supply solution. the circuit design includes provisions for features such as frequency synchronization, shutdown, and feedback controls for positive voltage regulation. these parts are pin ? to ? pin compatible with lt1372/1373. features ? integrated power switch: 1.5 a guaranteed ? wide input range: 2.7 v to 30 v ? high frequency allows for small components ? minimum external components ? easy external synchronization ? built in overcurrent protection ? frequency foldback reduces component stress during an overcurrent condition ? thermal shutdown with hysteresis ? shut down current: 50 a maximum ? pin ? to ? pin compatible with lt1372/1373 ? ncv prefix for automotive and other applications requiring unique site and control change requirements ? ? 40 ? c to 125 ? c ? these are pb ? free devices 517xe = specific device code x = 1 or 3 a = assembly location l = wafer lot y = year w = work week = pb ? free package soic ? 8 d suffix case 751 v cc ss 1 517xe alyw 8 agnd test pgnd fb v sw v c marking diagram and pin connections http://onsemi.com device package shipping ? ordering information ncv5171edr2g soic ? 8 (pb ? free) 2500 units / box ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. ncv5173edr2g soic ? 8 (pb ? free) 2500 units / box
ncv5171, ncv5173 http://onsemi.com 2 + ncv5171/73 1 2 3 45 6 7 8 v out l1 5 v c3 22 f v c fb test ss v cc agnd pgnd v sw + mbrs120t3 d1 22 h c2 22 f r3 1.28 k 3.72 k r2 c1 ss 3.3 v r1 5 k 0.01 f figure 1. applications diagram maximum ratings rating value unit junction temperature range, t j ? 40 to +150 ? c storage temperature range, t storage ? 65 to +150 ? c package thermal resistance junction ? to ? case, r jc junction ? to ? ambient, r ja 45 165 ? c/w lead temperature soldering: reflow (note 1) 260 peak (note 1) ? c esd, human body model 1.2 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 ? 180 seconds minimum above 237 ? c. maximum ratings pin name pin symbol v max v min i source i sink ic power input v cc 35 v ? 0.3 v n/a 200 ma shutdown/sync ss 30 v ? 0.3 v 1.0 ma 1.0 ma loop compensation v c 6.0 v ? 0.3 v 10 ma 10 ma voltage feedback input fb 10 v ? 0.3 v 1.0 ma 1.0 ma test pin test 6.0 v ? 0.3 v 1.0 ma 1.0 ma power ground pgnd 0.3 v ? 0.3 v 4 a 10 ma analog ground agnd 0 v 0 v n/a 10 ma switch input v sw 40 v ? 0.3 v 10 ma 3.0 a
ncv5171, ncv5173 http://onsemi.com 3 electrical characteristics (2.7 v< v cc < 30 v; ? 40 ? c < t j < 125 ? c unless otherwise stated.) characteristic test conditions min typ max unit positive and negative error amplifiers fb reference voltage v c tied to fb; measure at fb 1.246 1.276 1.300 v fb input current fb = v ref ? 1.0 0.1 1.0 a fb reference voltage line regulation v c = fb ? 0.01 0.03 %/v positive error amp transconductance i vc = ? 25 a 300 550 800 mho positive error amp gain (note 2) 200 500 ? v/v v c source current fb = 1.0 v, v c = 1.25 v 25 50 90 a v c sink current fb = 1.5 v, v c = 1.25 v 200 625 1500 a v c high clamp voltage fb = 1.0 v; v c sources 25 a 1.5 1.7 1.9 v v c low clamp voltage fb = 1.5 v; v c sinks 25 a 0.25 0.50 0.65 v v c threshold reduce v c from 1.5 v until switching stops 0.6 1.05 1.30 v oscillator base operating frequency ncv5171, fb = 1 v 230 280 310 khz base operating frequency ncv5173, fb = 1 v 460 560 620 khz reduced operating frequency ncv5171, fb = 0 v 30 52 120 khz reduced operating frequency ncv5173, fb = 0 v 60 104 160 khz maximum duty cycle ncv5171 90 94 ? % maximum duty cycle ncv5173 82 90 ? % fb frequency shift threshold frequency drops to reduced operating frequency 0.36 0.40 0.44 v sync/ shutdown sync range ncv5171 320 ? 500 khz sync range ncv5173 640 ? 1000 khz sync pulse transition threshold rise time = 20 ns 2.5 ? ? v ss bias current ss = 0 v ss = 3.0 v ? 15 ? ? 3.0 3.0 ? 8.0 a shutdown threshold ? 0.40 0.85 1.20 v shutdown delay 2.7 v ? v cc ? 12 v 12 v < v cc ? 30 v 12 12 80 36 350 200 s 2. guaranteed by design, not 100% tested in production.
ncv5171, ncv5173 http://onsemi.com 4 electrical characteristics (2.7 v< v cc < 30 v; ? 40 ? c < t j < 125 ? c unless otherwise stated.) characteristic unit max typ min test conditions power switch switch saturation voltage i switch = 1.5 a, (note 3) i switch = 1.0 a, 0 ? c ? t j ? 85 ? c i switch = 1.0 a, ? 40 ? c ? t j ? 0 ? c i switch = 10 ma ? ? ? ? 0.8 0.55 0.75 0.09 1.4 ? ? 0.45 v switch current limit 50% duty cycle, (note 3) 80% duty cycle, (note 3) 1.6 1.5 1.9 1.7 2.4 2.2 a minimum pulse width fb = 0 v, i sw = 4.0 a, (note 3) 200 250 300 ns i cc / iv sw 2.7 v ? v cc ? 12 v, 10 ma ? i sw ? 1.0 a 12 v < v cc ? 30 v, 10 ma ? i sw ? 1.0 a 2.7 v ? v cc ? 12 v, 10 ma ? i sw ? 1.5 a, (note 3) 12 v < v cc ? 30 v, 10 ma ? i sw ? 1.5 a, (note 3) ? ? ? ? 10 ? 17 ? 30 100 30 100 ma/a switch leakage v sw = 40 v, v cc = 0v ? 2.0 100 a general operating current i sw = 0 ? 5.5 8.0 ma shutdown mode current v c < 0.8 v, ss = 0 v, 2.7 v ? v cc ? 12 v v c < 0.8 v, ss = 0 v, 12 v ? v cc ? 30 v ? ? 12 ? 60 100 a minimum operation input voltage v sw switching, maximum i sw = 10 ma ? 2.45 2.70 v thermal shutdown (note 3) 150 180 210 ? c thermal hysteresis (note 3) ? 25 ? ? c 3. guaranteed by design, not 100% tested in production. package pin description package pin # pin symbol function 1 v c loop compensation pin. the v c pin is the output of the error amplifier and is used for loop compensation, current limit and soft start. loop compensation can be implemented by a simple rc network as shown in the application diagram on page 2 as r1 and c1. 2 fb positive regulator feedback pin. this pin senses a positive output voltage and is referenced to 1.276 v. when the voltage at this pin falls below 0.4 v, chip switching frequency reduces to 20% of the nominal frequency. 3 test these pins are connected to internal test logic and should either be left floating or tied to ground. connection to a voltage between 2 v and 6 v shuts down the internal oscillator and leaves the power switch running. 4 ss synchronization and shutdown pin. this pin may be used to synchronize the part to nearly twice the base frequency. a ttl low will shut the part down and put it into low current mode. if synchronization is not used, this pin should be either tied high or left floating for normal operation. 5 v cc input power supply pin. this pin supplies power to the part and should have a bypass capacitor connected to agnd. 6 agnd analog ground. this pin provides a clean ground for the controller circuitry and should not be in the path of large currents. the output voltage sensing resistors should be connected to this ground pin. this pin is connected to the ic substrate. 7 pgnd power ground. this pin is the ground connection for the emitter of the power switching transistor. connection to a good ground plane is essential. 8 v sw high current switch pin. this pin connects internally to the collector of the power switch. the open voltage across the power switch can be as high as 40 v. to minimize radiation, use a trace as short as practical.
ncv5171, ncv5173 http://onsemi.com 5 pgnd v sw + ? + ? v cc ss fb agnd positive error amp pwm compar- ator ramp summer slope compensation thermal shutdown 2.0 v regulator delay timer sync shutdown oscillator frequency shift 5:1 s pwm latch r q driver switch 63 m 0.4 v detector 1.276 v v c ? 5 figure 2. block diagram
ncv5171, ncv5173 http://onsemi.com 6 typical performance characteristics 0 temperature ( ? c) figure 3. i cc (no switching) vs. temperature current (ma) 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 v cc = 30 v 5.6 50 100 v cc = 12 v v cc = 2.7 v 0 temperature ( ? c) figure 4. i cc / iv sw vs. temperature (ma/a) 70 60 50 40 30 20 10 50 100 v cc = 30 v v cc = 12 v v cc = 2.7 v i sw = 1.5 a 0 i sw (ma) figure 5. v ce(sat) vs. i sw v ce(sat) (mv) 1200 1000 800 600 400 200 0 500 1000 ? 40 ? c 85 ? c 25 ? c temperature ( ? c) figure 6. minimum input voltage vs. temperature v in (v) 1.5 1.6 1.7 1.8 1.9 0 100 50 temperature ( ? c) figure 7. switching frequency vs. temperature (ncv5171) f osc (khz) 255 260 265 270 275 0 100 50 280 285 0 v fb (mv) f osc (% of typical) 100 75 50 25 350 v cc = (12 v) 380 400 420 450 85 ? c 25 ? c ? 40 ? c figure 8. switching frequency vs. temperature (ncv5173) figure 9. switching frequency vs. v fb temperature ( ? c) f osc (khz) 540 545 550 555 560 0 100 50 565 570 535 530 525 520
ncv5171, ncv5173 http://onsemi.com 7 typical performance characteristics temperature ( ? c) v o lt age (v) 1.268 1.270 1.272 1.274 1.276 0 100 50 1.278 1.280 v cc = 12 v v cc = 2.7 v v cc = 30 v temperature ( ? c) i fb ( a) 0.08 0.10 0.12 0.14 0.16 0 100 50 0.18 0.20 figure 10. reference voltage vs. temperature figure 11. i fb vs. temperature temperature ( ? c) current (a) 2.20 2.30 2.40 2.50 0 100 50 2.60 v cc = 12 v v cc = 30 v v cc = 2.7 v temperature ( ? c) duty cycle (%) 95 96 97 98 0 100 50 99 v cc = 30 v v cc = 2.7 v 94 93 v cc = 12 v figure 12. current limit vs. temperature figure 13. maximum duty cycle vs. temperature temperature ( ? c) voltage (v) 0.5 0.6 0.7 0.8 0.9 0 50 1.0 1.1 0.4 temperature ( ? c) voltage (v) 0.7 0.9 1.1 1.3 0 100 50 1.5 1.7 v c high clamp voltage v c threshold figure 14. v c threshold and high clamp voltage vs. temperature figure 15. shutdown threshold vs. temperature
ncv5171, ncv5173 http://onsemi.com 8 typical performance characteristics temperature ( ? c) delay ( s) 80 100 120 140 0 100 50 160 v cc = 12 v v cc = 30 v v cc = 2.7 v 60 40 v ss (v) i ss ( a) 10 20 30 40 17 5 ? 40 ? c 0 ? 10 85 ? c 25 ? c 39 figure 16. shutdown delay vs. temperature figure 17. i ss vs. v ss v in (v) i cc ( a) 20 30 40 10 ? 40 ? c 10 0 85 ? c 25 ? c temperature ( ? c) g m ( mho) 450 500 0 100 50 550 600 figure 18. i cc vs. v in during shutdown figure 19. error amplifier transconductance vs. temperature v ref ? v fb (mv) i out ( a) 20 60 100 0 ? 20 ? 60 25 ? 25 ? 75 ? 125 ? 175 ? 255 temperature ( ? c) current ( a) 2.6 0 100 50 2.5 2.4 2.3 2.2 2.1 2.0 figure 20. error amplifier i out vs. v fb figure 21. switch leakage vs. temperature
ncv5171, ncv5173 http://onsemi.com 9 applications information theory of operation current mode control + ? driver c o r load v sw x5 summer slope compensation v c oscillator d1 v cc s r q in out pwm compar - ator l 63 m figure 22. current mode control scheme power switch the ncv5171/73 boost regulator incorporates a current mode control scheme, in which the pwm ramp signal is derived from the power switch current. this ramp signal is compared to the output of the error amplifier to control the on ? time of the power switch. the oscillator is used as a fixed ? frequency clock to ensure a constant operational frequency. the resulting control scheme features several advantages over conventional voltage mode control. first, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. this eliminates the delay caused by the output filter and error amplifier, which is commonly found in voltage mode controllers. the second benefit comes from inherent pulse ? by ? pulse current limiting by merely clamping the peak switching current. finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. this allows both a simpler compensation and a higher gain ? bandwidth over a comparable voltage mode circuit. without discrediting its apparent merits, current mode control comes with its own peculiar problems, mainly, subharmonic oscillation at duty cycles over 50%. ncv5171/73 solves this problem by adopting a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. a proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. oscillator and shutdown figure 23. timing diagram of sync and shutdown v sw current ramp sync the oscillator is trimmed to guarantee an 18% frequency accuracy. the output of the oscillator turns on the power switch at a frequency of 280 khz (ncv5171) or 560 khz (ncv5173) as shown in figure 22. the power switch is turned off by the output of the pwm comparator. a ttl ? compatible sync input at the ss pin is capable of syncing up to 1.8 times the base oscillator frequency. as shown in figure 23, in order to sync to a higher frequency, a positive transition turns on the power switch before the output of the oscillator goes high, thereby resetting the oscillator. the sync operation allows multiple power supplies to operate at the same frequency. a sustained logic low at the ss pin will shut down the ic and reduce the supply current. an additional feature includes frequency shift to 20% of the nominal frequency when the fb pin triggers the threshold. during power up, overload, or short circuit conditions, the minimum switch on ? time is limited by the pwm comparator minimum pulse width. extra switch off ? time reduces the minimum duty cycle to protect external components and the ic itself. as previously mentioned, this block also produces a ramp for the slope compensation to improve regulator stability. error amplifier + ? ncv5171/73 figure 24. error amplifier equivalent circuit 1m positive error ? amp 1.276 v fb v c c1 r1 5 k 0.01 f voltage clamp 120 pf the fb pin is directly connected to the inverting input of the positive error amplifier, whose non ? inverting input is fed by the 1.276 v reference. it is a transconductance amplifier with a high output impedance of approximately 1 m , as shown in figure 24. the v c pin is connected to the output of the error amplifiers and is internally clamped between 0.5 v and 1.7 v. a typical connection at the v c pin includes a capacitor in series with a resistor to ground, forming a pole/zero for loop compensation. an external shunt can be connected between the v c pin and ground to reduce its clamp voltage. consequently, the current limit of the internal power transistor current is reduced from its nominal value.
ncv5171, ncv5173 http://onsemi.com 10 switch driver and power switch the switch driver receives a control signal from the logic section to drive the output power switch. the switch is grounded through emitter resistors (63 m total) to the pgnd pin. pgnd is not connected to the ic substrate so that switching noise can be isolated from the analog ground. the peak switching current is clamped by an internal circuit. the clamp current is guaranteed to be greater than 1.5 a and varies with duty cycle due to slope compensation. the power switch can withstand a maximum voltage of 40 v on the collector (v sw pin). the saturation voltage of the switch is typically less than 1 v to minimize power dissipation. short circuit condition when a short circuit condition happens in a boost circuit, the inductor current will increase during the whole switching cycle, causing excessive current to be drawn from the input power supply. since control ics don?t have the means to limit load current, an external current limit circuit (such as a fuse or relay) has to be implemented to protect the load, power supply and ics. in other topologies, the frequency shift built into the ic prevents damage to the chip and external components. this feature reduces the minimum duty cycle and allows the transformer secondary to absorb excess energy before the switch turns back on. figure 25. startup waveforms of circuit shown in the application diagram. load = 400 ma. i l v out v c v cc the ncv5171/73 can be activated by either connecting the v cc pin to a voltage source or by enabling the ss pin. startup waveforms shown in figure 25 are measured in the boost converter demonstrated in the application diagram on the page 2 of this document. recorded after the input voltage is turned on, this waveform shows the various phases during the power up transition. when the v cc voltage is below the minimum supply voltage, the v sw pin is in high impedance. therefore, current conducts directly from the input power source to the output through the inductor and diode. once v cc reaches approximately 1.5 v, the internal power switch briefly turns on. this is a part of the ncv5171/73?s normal operation. the turn ? on of the power switch accounts for the initial current swing. when the v c pin voltage rises above the threshold, the internal power switch starts to switch and a voltage pulse can be seen at the v sw pin. detecting a low output voltage at the fb pin, the built ? in frequency shift feature reduces the switching frequency to a fraction of its nominal value, reducing the minimum duty cycle, which is otherwise limited by the minimum on ? time of the switch. the peak current during this phase is clamped by the internal current limit. when the fb pin voltage rises above 0.4 v, the frequency increases to its nominal value, and the peak current begins to decrease as the output approaches the regulation voltage. the overshoot of the output voltage is prevented by the active pull ? on, by which the sink current of the error amplifier is increased once an overvoltage condition is detected. the overvoltage condition is defined as when the fb pin voltage is 50 mv greater than the reference voltage. component selection frequency compensation the goal of frequency compensation is to achieve desirable transient response and dc regulation while ensuring the stability of the system. a typical compensation network, as shown in figure 26, provides a frequency response of two poles and one zero. this frequency response is further illustrated in the bode plot shown in figure 27. ncv5171/73 figure 26. a typical compensation network v c gnd c1 r1 c2 the high dc gain in figure 27 is desirable for achieving dc accuracy over line and load variations. the dc gain of a transconductance error amplifier can be calculated as follows: gain dc g m r o where: g m = error amplifier transconductance; r o = error amplifier output resistance ? 1 m . the low frequency pole, f p1, is determined by the error amplifier output resistance and c1 as: f p1 1 2 c1r o
ncv5171, ncv5173 http://onsemi.com 11 the first zero generated by c1 and r1 is: f z1 1 2 c1r1 the phase lead provided by this zero ensures that the loop has at least a 45 ? phase margin at the crossover frequency. therefore, this zero should be placed close to the pole generated in the power stage which can be identified at frequency: f p 1 2 c o r load where: c o = equivalent output capacitance of the error amplifier ? 120 pf; r load = load resistance. the high frequency pole, f p2 , can be placed at the output filter?s esr zero or at half the switching frequency. placing the pole at this frequency will cut down on switching noise. the frequency of this pole is determined by the value of c2 and r1: f p2 1 2 c2r1 one simple method to ensure adequate phase margin is to design the frequency response with a ? 20 db per decade slope, until unity ? gain crossover. the crossover frequency should be selected at the midpoint between f z1 and f p2 where the phase margin is maximized. figure 27. bode plot of the compensation network shown in figure 26 frequency (log) f p1 gain (db) dc gain f z1 f p2 v sw voltage limit in the boost topology, v sw pin maximum voltage is set by the maximum output voltage plus the output diode forward voltage. the diode forward voltage is typically 0.5 v for schottky diodes and 0.8 v for ultrafast recovery diodes v sw(max) v out(max) v f where: v f = output diode forward voltage. in the flyback topology, peak v sw voltage is governed by: v sw(max) v cc(max) (v out v f ) n where: n = transformer turns ratio, primary over secondary. when the power switch turns off, there exists a voltage spike superimposed on top of the steady ? state voltage. usually this voltage spike is caused by transformer leakage inductance charging stray capacitance between the v sw and pgnd pins. to prevent the voltage at the v sw pin from exceeding the maximum rating, a transient voltage suppressor in series with a diode is paralleled with the primary windings. another method of clamping switch voltage is to connect a transient voltage suppressor between the v sw pin and ground. magnetic component selection when choosing a magnetic component, one must consider factors such as peak current, core and ferrite material, output voltage ripple, emi, temperature range, physical size and cost. in boost circuits, the average inductor current is the product of output current and voltage gain (v out /v cc ), assuming 100% energy transfer efficiency. in continuous conduction mode, inductor ripple current is i ripple v cc (v out v cc ) (f)(l)(v out) where: f = 280 khz (ncv5171) or 560 khz (ncv5173). the peak inductor current is equal to average current plus half of the ripple current, which should not cause inductor saturation. the above equation can also be referenced when selecting the value of the inductor based on the tolerance of the ripple current in the circuits. small ripple current provides the benefits of small input capacitors and greater output current capability. a core geometry like a rod or barrel is prone to generating high magnetic field radiation, but is relatively cheap and small. other core geometries, such as toroids, provide a closed magnetic loop to prevent emi. input capacitor selection in boost circuits, the inductor becomes part of the input filter, as shown in figure 29. in continuous mode, the input current waveform is triangular and does not contain a large pulsed current, as shown in figure 28. this reduces the requirements imposed on the input capacitor selection. during continuous conduction mode, the peak to peak inductor ripple current is given in the previous section. as we can see from figure 28, the product of the inductor current ripple and the input capacitor?s effective series resistance (esr) determine the v cc ripple. in most applications, input capacitors in the range of 10 f to 100 f with an esr less than 0.3 work well up to a full 1.5 a switch current.
ncv5171, ncv5173 http://onsemi.com 12 v cc ripple figure 28. boost input voltage and current ripple waveforms i in i l + ? figure 29. boost circuit effective input filter v cc c in r esr i l i in the situation is different in a flyback circuit. the input current is discontinuous and a significant pulsed current is seen by the input capacitors. therefore, there are two requirements for capacitors in a flyback regulator: energy storage and filtering. to maintain a stable voltage supply to the chip, a storage capacitor larger than 20 f with low esr is required. to reduce the noise generated by the inductor, insert a 1.0 f ceramic capacitor between v cc and ground as close as possible to the chip. output capacitor selection figure 30. typical output voltage ripple v out ripple i l by examining the waveforms shown in figure 30, we can see that the output voltage ripple comes from two major sources, namely capacitor esr and the charging/discharging of the output capacitor. in boost circuits, when the power switch turns off, i l flows into the output capacitor causing an instant v = i in ? esr. at the same time, current i l ? i out charges the capacitor and increases the output voltage gradually. when the power switch is turned on, i l is shunted to ground and i out discharges the output capacitor. when the i l ripple is small enough, i l can be treated as a constant and is equal to input current i in . summing up, the output voltage peak ? peak ripple can be calculated by: v out(ripple) (i in i out) (1 d) (c out) (f) i out d (c out )(f) i in esr the equation can be expressed more conveniently in terms of v cc , v out and i out for design purposes as follows: v out(ripple) i out (v out v cc ) (c out )(f) 1 (c out )(f) (i out )(v out )(esr) v cc the capacitor rms ripple current is: i ripple (i in i out ) 2 (1 d) (i out ) 2 (d) i out v out v cc v cc although the above equations apply only for boost circuits, similar equations can be derived for flyback circuits.
ncv5171, ncv5173 http://onsemi.com 13 reducing the current limit in some applications, the designer may prefer a lower limit on the switch current than 1.5 a. an external shunt can be connected between the v c pin and ground to reduce its clamp voltage. consequently, the current limit of the internal power transistor current is reduced from its nominal value. the voltage on the v c pin can be evaluated with the equation v c i sw r e a v where: r e = 0.063 , the value of the internal emitter resistor; a v = 5 v/v, the gain of the current sense amplifier. since r e and a v cannot be changed by the end user, the only available method for limiting switch current below 1.5 a is to clamp the v c pin at a lower voltage. if the maximum switch or inductor current is substituted into the equation above, the desired clamp voltage will result. a simple diode clamp, as shown in figure 31, clamps the v c voltage to a diode drop above the voltage on resistor r3. unfortunately, such a simple circuit is not generally acceptable if v in is loosely regulated. figure 31. current limiting using a diode clamp v c d1 v cc r1 v in c2 c1 r2 r3 another solution to the current limiting problem is to externally measure the current through the switch using a sense resistor. such a circuit is illustrated in figure 32. ? + figure 32. current limiting using a current sense resistor v c r sense q1 v cc r1 v in c2 c1 r2 c3 output ground pgnd agnd the switch current is limited to i switch(peak) v be(q1) r sense where: v be(q1) = the base ? emitter voltage drop of q1, typically 0.65 v. the improved circuit does not require a regulated voltage to operate properly. unfortunately, a price must be paid for this convenience in the overall efficiency of the circuit. the designer should note that the input and output grounds are no longer common. also, the addition of the current sense resistor, r sense , results in a considerable power loss which increases with the duty cycle. resistor r2 and capacitor c3 form a low ? pass filter to remove noise.
ncv5171, ncv5173 http://onsemi.com 14 subharmonic oscillation subharmonic oscillation (shm) is a problem found in current ? mode control systems, where instability results when duty cycle exceeds 50%. shm only occurs in switching regulators with a continuous inductor current. this instability is not harmful to the converter and usually does not affect the output voltage regulation. shm will increase the radiated em noise from the converter and can cause, under certain circumstances, the inductor to emit high ? frequency audible noise. shm is an easily remedied problem. the rising slope of the inductor current is supplemented with internal ?slope compensation? to prevent any duty cycle instability from carrying through to the next switching cycle. in ncv5171/73, the slope compensation is added during the entire switch on ? time, typically in the amount of 180 ma/ s. in some cases, shm can rear its ugly head despite the presence of the onboard slope compensation. the simple cure to this problem is more slope compensation to avoid the unwanted oscillation. in that case, an external circuit, shown in figure 33, can be added to increase the amount of slope compensation used. this circuit requires only a few components and is ?tacked on? to the compensation network. figure 33. technique for increasing slope compensation v c r1 c2 c1 r2 r3 v sw c3 v sw the dashed box contains the normal compensation circuitry to limit the bandwidth of the error amplifier. resistors r2 and r3 form a voltage divider off of the v sw pin. in normal operation, v sw looks similar to a square wave, and is dependent on the converter topology. formulas for calculating v sw in the boost and flyback topologies are given in the section ?v sw voltage limit.? the voltage on v sw charges capacitor c3 when the switch is off, causing the voltage at the v c pin to shift upwards. when the switch turns on, c3 discharges through r3, producing a negative slope at the v c pin. this negative slope provides the slope compensation. the amount of slope compensation added by this circuit is: i t v sw r 3 r 2 r 3 1 e (1 d) r 3 c 3 f sw f sw (1 d)r e a v where: i/ t = the amount of slope compensation added (a/s); v sw = the voltage at the switch node when the transistor is turned off (v); f sw = the switching frequency, typically 280 khz (ncv5171) or 560 khz (ncv5173) d = the duty cycle; r e = 0.063 , the value of the internal emitter resistor; a v = 5 v/v, the gain of the current sense amplifier. in selecting appropriate values for the slope compensation network, the designer is advised to choose a convenient capacitor, then select values for r2 and r3 such that the amount of slope compensation added is 100 ma/ s. then r2 may be increased or decreased as necessary. of course, the series combination of r2 and r3 should be large enough to avoid drawing excessive current from v sw . additionally, to ensure that the control loop stability is improved , the time constant formed by the additional components should be chosen such that r 3 c 3 1 d f sw finally, it is worth mentioning that the added slope compensation is a tradeoff between duty cycle stability and transient response. the more slope compensation a designer adds, the slower the transient response will be, due to the external circuitry interfering with the proper operation of the error amplifier. soft ? start through the addition of an external circuit, a soft ? start function can be added to the ncv5171/73 family of components. soft ? start circuitry prevents the v c pin from slamming high during startup, thereby inhibiting the inductor current from rising at a high slope.
ncv5171, ncv5173 http://onsemi.com 15 this circuit, shown in figure 34, requires a minimum number of components and allows the soft ? start circuitry to activate any time the ss pin is used to restart the converter. figure 34. soft start v c r1 c2 c1 d2 d1 v cc c3 v in ss ss resistor r1 and capacitors c1 and c2 form the compensation network. at turn on, the voltage at the v c pin starts to come up, charging capacitor c3 through schottky diode d2, clamping the voltage at the v c pin such that switching begins when v c reaches the v c threshold, typically 1.05 v (refer to graphs for detail over temperature). v c v f(d2) v c3 therefore, c3 slows the startup of the circuit by limiting the voltage on the v c pin. the soft ? start time increases with the size of c3. diode d1 discharges c3 when ss is low. if the shutdown function is not used with this part, the cathode of d1 should be connected to v in . calculating junction temperature to ensure safe operation of ncv5171/73, the designer must calculate the on ? chip power dissipation and determine its expected junction temperature. internal thermal protection circuitry will turn the part off once the junction temperature exceeds 180 ? c ? 30 ? . however, repeated operation at such high temperatures will ensure a reduced operating life. calculation of the junction temperature is an imprecise but simple task. first, the power losses must be quantified. there are three major sources of power loss on the ncv5171/73: ? biasing of internal control circuitry, p bias ? switch driver, p driver ? switch saturation, p sat the internal control circuitry, including the oscillator and linear regulator, requires a small amount of power even when the switch is turned off. the specifications section of this datasheet reveals that the typical operating current, i q , due to this circuitry is 5.5 ma. additional guidance can be found in the graph of operating current vs. temperature. this graph shows that iq is strongly dependent on input voltage, v in , and temperature. then p bias v in i q since the onboard switch is an npn transistor, the base drive current must be factored in as well. this current is drawn from the v in pin, in addition to the control circuitry current. the base drive current is listed in the specifications as i cc / i sw , or switch transconductance. as before, the designer will find additional guidance in the graphs. with that information, the designer can calculate p driver v in i sw i cc i sw d where: i sw = the current through the switch; d = the duty cycle or percentage of switch on ? time. i sw and d are dependent on the type of converter. in a boost converter, i sw(avg)
i l ( avg ) d 1 efficiency d
v out v in v out in a flyback converter, i sw(avg)
v out i load v in 1 efficiency 1 d d
v out v out n s n p v in the switch saturation voltage, v (ce)sat , is the last major source of on ? chip power loss. v (ce)sat is the collector ? emitter voltage of the internal npn transistor when it is driven into saturation by its base drive current. the value for v (ce)sat can be obtained from the specifications or from the graphs, as ?switch saturation voltage.? thus, p sat
v (ce)sat i sw d finally, the total on ? chip power losses are p d p bias p driver p sat power dissipation in a semiconductor device results in the generation of heat in the junctions at the surface of the chip. this heat is transferred to the surface of the ic package, but a thermal gradient exists due to the resistive properties of the package molding compound. the magnitude of the thermal gradient is expressed in manufacturers? data sheets as ja , or junction ? to ? ambient thermal resistance. the on ? chip junction temperature can be calculated if ja , the air temperature near the surface of the ic, and the on ? chip power dissipation are known.
ncv5171, ncv5173 http://onsemi.com 16 t j t a (p d ja ) where: t j = ic or fet junction temperature ( ? c); t a = ambient temperature ( ? c); p d = power dissipated by part in question (w); ja = junction ? to ? ambient thermal resistance ( ? c/w). for the ncv5171/73, ja =165 ? c/w. once the designer has calculated t j , the question of whether the ncv5171/73 can be used in an application is settled. if t j exceeds 150 ? c, the absolute maximum allowable junction temperature, the ncv5171/73 is not suitable for that application. if t j approaches 150 ? c, the designer should consider possible means of reducing the junction temperature. perhaps another converter topology could be selected to reduce the switch current. increasing the airflow across the surface of the chip might be considered to reduce t a . circuit layout guidelines in any switching power supply, circuit layout is very important for proper operation. rapidly switching currents combined with trace inductance generates voltage transitions that can cause problems. therefore the following guidelines should be followed in the layout. 1. in boost circuits, high ac current circulates within the loop composed of the diode, output capacitor, and on ? chip power transistor. the length of associated traces and leads should be kept as short as possible. in the flyback circuit, high ac current loops exist on both sides of the transformer. on the primary side, the loop consists of the input capacitor, transformer, and on ? chip power transistor, while the transformer, rectifier diodes, and output capacitors form another loop on the secondary side. just as in the boost circuit, all traces and leads containing large ac currents should be kept short. 2. separate the low current signal grounds from the power grounds. use single point grounding or ground plane construction for the best results. 3. locate the voltage feedback resistors as near the ic as possible to keep the sensitive feedback wiring short. connect feedback resistors to the low current analog ground.
ncv5171, ncv5173 http://onsemi.com 17 ncv5171/73 3.3 v in v c (1 ) fb (2) 0.1 f v cc (5) agnd (6) pgnd (7) v sw (8) 200 pf mbrs120t3 22 f 22 h figure 35. additional application diagram, 3.3 v input, 5.0 v/ 400 ma output boost converter 10 f gnd 5.0 k 3.6 k gnd 5.0 v o 1.3 k + + + ncv5171/73 +12 v v c (1 ) fb (2) v cc (5) agnd (6) pgnd (7) v sw (8) mbrs140t3 22 f 47 f figure 36. additional application diagram, 2.7 to 13 v input, 12 v/ 200 ma output flyback converter 1.0 f gnd 2.0 k 10.72 k gnd 1.28 k 47 f 47 nf 4.7 nf v cc ? 12 v t1 1:2 p6ke ? 15a 1n4148 mbrs140t3 ncv5171/73 v c (1 ) fb (2) v cc (5) agnd (6) pgnd (7) v sw (8) 2.2 f figure 37. additional application diagram, ? 9.0 v to ? 28 v input, ? 5.0 v/700 ma output inverted buck converter 15 h gnd 300 gnd 5.0 k .01 f 200 pf v in ? 5.0 v out 1.1 k 22 f low esr
ncv5171, ncv5173 http://onsemi.com 18 ncv5171/73 + + v c (1 ) fb (2) v cc (5) agnd (6) pgnd (7) v sw (8) 22 f figure 38. additional application diagram, 2.7 v to 28 v input, 5.0 v output sepic converter gnd 12.76 k gnd 5.0 k .01 f 200 pf v cc 22 h low esr 22 f 22 h 22 f 37.24 k 5.0 v ncv5171/73 v c fb agnd pgnd v sw figure 39. additional application diagram, 4.0 v input, 100 v/ 10 ma output boost converter with output voltage multiplier gnd gnd .01 v cc 4.0 v test ss 1 2 3 4 8 7 6 5 c11 r1 r2 r3 c10 .1 c8 c9 c1 c2 c3 c4 c5 c6 c7 .1 .1 .1 .1 50 v 50 v 50 v 50 v .1 50 v .1 50 v .1 50 v d1 d1 d1 d1 d1 d1 d1 1n4148 1n4148 1n4148 1n4148 1n4148 1n4148 1n4148 99.755 k/0.1 w, 1% 1.245 k/0.1 w, 1% 2.0 k .1 10 100 v o + + + ncv5171/73 v c fb v cc agnd pgnd v sw figure 40. additional application diagram, 5.0 v input, ? 12 v output dual boost converter gnd gnd 0.01 f 200 pf 22 f 15 h 22 f 1.28 k 5.0 k ss test 1 2 3 45 6 7 8 +5.0 v ss c6 c1 r1 r2 r3 10.72 k c5 22 f c3 d3 d2 l1 d1 ? 12 v +12 v c4 0.1 f
ncv5171, ncv5173 http://onsemi.com 19 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv5171/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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